run 50 ns
#KERNEL: stopped at delta: 5000 at time 10 ns.
#KERNEL: Error: KERNEL_0160 Delta count overflow. Increase the iteration limit using -i argument for asim or the matching entry in simulation preferences.
#Error: Fatal error occurred during simulation.Ошибка моделирования VHDL: «переполнение переполнения дельта»
Где я ошибаюсь?
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity funct is
port(x: in std_logic_vector (2 downto 1);
y: out std_logic);
end funct;
architecture funct of funct is
signal r, s, q : std_logic_vector(2 downto 0) := "000";
begin
process
begin
wait on x, q;
r(2) <= not(q(0)) or (not(q(1)) and x(2) and not(x(1)));
r(1) <= q(2) and not(x(2));
r(0) <= not(q(1)) and q(0) and x(1);
s(2) <= q(1) and x(2);
s(1) <= not(q(2)) and q(0) and not(x(2));
s(0) <= not(q(2)) and not(q(1)) and not(q(0)) and x(2);
end process;
y <= q(2) and not(q(1)) and q(0);
process
begin
wait on r, s;
q(0) <= s(0) or (not(r(0)) and q(0));
q(1) <= s(1) or (not(r(1)) and q(1));
q(2) <= s(2) or (not(r(2)) and q(2));
end process;
end funct;