-1
module clock
(
input logic wclk,rclk
);
initial begin
wclk = 1'b0;
rclk = 1'b0;
end
task genclock;
begin
genvar i;
generate
begin
for(i=0;i<20;i++)
begin
#10
wclk=~wclk;
rclk=~rclk;
#20
rclk=~rclk;
#20
wclk=~wclk;
#40
wclk=~wclk;
#40
rclk=~rclk;
#80
wclk=~wclk;
#100
rclk=~rclk;
#10
wclk=~wclk;
#2
rclk=~rclk;
#150
wclk=~wclk;
rclk=~rclk;
#30
wclk=~wclk;
#44
rclk=~rclk;
end
#100
$finish;
end
endgenerate
end
endtask
endmodule